View MAX8855AETJ_2600925.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

general description the max8855/max8855a high-efficiency, dual step-down regulators are capable of delivering up to 5a at each out- put. the devices operate from a 2.30v to 3.6v supply, and provide output voltages from 0.6v to 0.9 x v in , making them ideal for on-board point-of-load applications. total output error is less than 1% over load, line, and temperature. the max8855/max8855a operate in pwm mode with a switching frequency ranging from 0.5mhz to 2mhz, set by an external resistor. it can also be synchronized to an external clock in the same frequency range. two internal switching regulators operate 180 out-of-phase to reduce the input ripple current, and consequently reduce the required input capacitance. the high operating frequency minimizes the size of external components. high efficiency, internal dual-nmos design keeps the board cool under heavy loads. the voltage-mode control architecture and the high-band- width (> 15mhz typ) voltage-error amplifier allow a type iii compensation scheme to be utilized to achieve fast response under both line and load transients, and also allow for ceramic output capacitors. programmable soft-start reduces input inrush current. two enable inputs allow the turning on/off of each out- put individually, resulting in great flexibility for system- level designs. a reference input is provided to facilitate output-voltage tracking applications. the max8855/ max8855a are available in a 32-pin tqfn (5mm x 5mm) package with 0.8mm max height. applications asic/cpu/dsp power supplies ddr power supplies set-top box power supplies printer power supplies network power supplies features 27m ? on-resistance internal mosfets dual, 5a, pwm step-down regulators fully protected against overcurrent, short circuit, and overtemperature ?% output accuracy over load, line, and temperature operates from 2.30v to 3.6v supply refin on one channel for tracking or external reference integrated boost diodes adjustable output from 0.6v to 0.9 x v in soft-start reduces inrush supply current 0.5mhz to 2mhz adjustable switching, or fsync input all-ceramic-capacitor design 180 out-of-phase operation reduces input ripple current individual enable inputs and pwrgd outputs safe-start into prebiased output available in 5mm x 5mm thin qfn package sink/source current in ddr applications max8855/max8855a dual, 5a, 2mhz step-down regulators ________________________________________________________________ maxim integrated products 1 ordering information 19-0726; rev 3; 7/11 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. + denotes a lead(pb)-free/rohs-compliant package. * ep = exposed pad. evaluation kit available part temp range pin-package max8855etj+ -40c to +85c 32 tqfn-ep* MAX8855AETJ+ -40c to +85c 32 tqfn-ep* pin configuration appears at end of data sheet. fb2 en2 comp2 lx2 bst2 gnd pgnd2 input1 2.30v to 3.6v en1 bst1 comp1 fb1 pgnd1 lx1 in1 in2 type iii compensation output1 1.2v / 5a input2 2.30v to 3.6v pwrgd1 pwrgd2 off on max8855/ max8855a type iii compensation output2 1.5v / 5a off on typical operating circuit
max8855/max8855a dual, 5a, 2mhz step-down regulators 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v in_ = v vdd = v vdl = 3.3v, v fb_ = 0.5v, v ss_ = v refin = 600mv, pgnd_ = gnd, r fsync = 10k ? , l = 0.47h, c bst_ = 0.1f, c ss_ = 0.022f, pwrgd_ not connected; t a = -40c to +85c, typical values are at t a = +25c, unless otherwise noted.) (note 2) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. in_, lx_, v dd , vdl, pwrgd_ to gnd..................-0.3v to +4.5v v dd , vdl to in_.....................................................-0.3v to +4.5v en_, ss_, comp_, fb_, refin, fsync to gnd ......-0.3v to the lower of (v vdd + 0.3v) and (v vdl + 0.3v) continuous lx_ current (note 1) ...................................5.5a rms bst_ to lx_ ...........................................................-0.3v to +4.5v pgnd_ to gnd......................................................-0.3v to +0.3v continuous power dissipation (t a = +70c) 32-pin tqfn (5mm x 5mm) (derate 34.5mw/c above +70c) ..........................2758.6mw operating ambient temperature range .............-40c to +85c operating junction temperature range ...........-40c to +125c storage temperature range .............................-65c to +150c lead temperature (soldering, 10s) .................................+300c soldering temperature (reflow) .......................................+260c parameter conditions min typ max units in1, in2, vdl, vdd max8855 2.35 3.60 in_, vdl, and v dd voltage range (note 3) max8855a 2.30 3.60 v v in _ = 2.5v 1.9 3.5 in_ supply current 1mhz switching, no load v in _ = 3.3v 2.8 5 ma v vdd = 2.5v 7.2 v dd + vdl supply current 1mhz switching, v dd = vdl v vdd = 3.3v 10 15 ma t a = +25c 11 shutdown supply current (i in1 + i in2 + i vdd + i vdl ) v in _ = v vdd = v vdl = v b s t _ - v l x _ = 3.6v , v e n _ = 0v t a = +85c 0.3 a rising 2.0 2.2 in_, v dd undervoltage lockout threshold uvlo monitors v dd , in1, and in2 falling 1.8 1.9 v in_, v dd undervoltage lockout deglitch 2 s bst1, bst2 t a = +25c 2 shutdown bst_ current v in _ = v vd d = v vd l = v bs t _ = 3.6v, v en _ = 0v, v lx _ = 0 or 3.6v t a = +85c 0.02 a comp1, comp2 comp_ clamp voltage, high v vdd = v in _ = 2.3v to 3.6v, v fb _ = 0.7v 1.80 2.00 2.25 v comp_ slew rate 1.40 v/s comp_ shutdown resistance from comp_ to gnd, v en _ = 0v 7 25 ? note 1: lx_ have internal clamp diodes to pgnd_ and in_. applications that forward bias these diodes should take care not to exceed the ics package power-dissipation limits. note 2: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four- layer board. for detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial . package thermal characteristics (note 2) tqfn junction-to-ambient thermal resistance ( ja ) ...........29c/w junction-to-case thermal resistance ( jc ) ...............1.7c/w
max8855/max8855a dual, 5a, 2mhz step-down regulators _______________________________________________________________________________________ 3 parameter conditions min typ max units error amplifier v v d d = v i n _ = 2.5v to 3.3v ( m ax 8855) fb_ regulation voltage v c om p _ = 1v to 2v v v d d = v i n _ = 2.3v to 3.3v ( m ax 8855a) 0.594 0.600 0.606 v v v d d = v i n _ = 2.5v to 3.3v ( m ax 8855) fb_ regulation voltage with external reference v c om p _ = 1v to 2v v v d d = v i n _ = 2.3v to 3.3v ( m ax 8855a) 0.594 0.600 0.606 v error amplifier common-mode-input range 0 v vdd - 1.6 v error amplifier maximum output current 1 ma t a = +25c 40 300 fb_ input bias current v fb _ = 0.605v t a = +85c 37 na refin, ss2 t a = +25 c 90 500 refin input bias current v fb _ = 0.610v t a = +85 c65 na max8855 v vdd = 2.35v to 2.6v max8855a v vdd = 2.30v to 2.6v 0 v vdd - 1.65 refin common-mode range v vdd = 2.6v to 3.6v 0 v vdd - 1.70 v lx1, lx2 (all pins combined) v in _ = v bs t _ - v lx _ = 3.3v 31 52 lx_ on-resistance, high i lx_ = -2a v in _ = v bs t _ - v lx _ = 2.5v 34 m ? v in _ = 3.3v 27 46 lx_ on-resistance, low i lx_ = -2a v in _ = 2.5v 29 m ? lx_ current-limit threshold high-side sourcing and freewheeling 7.0 8.3 9.6 a t a = +25 c +0.1 v lx_ = 3.6v t a = +85 c-0.1 t a = +25 c -10 lx_ leakage current v in _ = 3.6v, v en _ = 0v v lx_ = 0v t a = +85 c-0.1 a r fsync = 10k ? 0.9 1.0 1.1 lx_ switching frequency r fsync = 4.75k ? 1.80 2.0 2.2 mhz lx_ minimum off-time 50 ns lx_ minimum on-time 95 ns lx_ maximum duty cycle r fsync = 10k ? 90 95 % maximum lx_ output current 3 a rms electrical characteristics (continued) (v in_ = v vdd = v vdl = 3.3v, v fb_ = 0.5v, v ss_ = v refin = 600mv, pgnd_ = gnd, r fsync = 10k ? , l = 0.47h, c bst_ = 0.1f, c ss_ = 0.022f, pwrgd_ not connected; t a = -40c to +85c, typical values are at t a = +25c, unless otherwise noted.) (note 2)
max8855/max8855a dual, 5a, 2mhz step-down regulators 4 _______________________________________________________________________________________ electrical characteristics (continued) (v in_ = v vdd = v vdl = 3.3v, v fb_ = 0.5v, v ss_ = v refin = 600mv, pgnd_ = gnd, r fsync = 10k ? , l = 0.47h, c bst_ = 0.1f, c ss_ = 0.022f, pwrgd_ not connected; t a = -40c to +85c, typical values are at t a = +25c, unless otherwise noted.) (note 2) parameter conditions min typ max units en1, en2 en_ logic-low 0.7 v en_ logic-high 1.7 v t a = +25 c-1 +1 en_ input current v en _ = 0 or 3.6v, v vdd = 3.6v t a = +85 c 0.01 a ss1, ss2 ss_ charging current v ss _ = 300mv 5 8 11 a refin, ss2 discharge resistance in shutdown or a fault condition 335 ? thermal shutdown thermal-shutdown threshold (independent channels) +165 c thermal-shutdown hysteresis 20 c note 2: all devices 100% production tested at t a = +25c. limits over temperature are guaranteed by design. note 3: v vdd must equal v vdl and be equal to or greater than v in _. efficiency vs. load current with 3.3v input max8855/max8855a toc01 load current (ma) efficiency (%) 1000 10 20 30 40 50 60 70 80 90 100 0 100 10,000 v out_ = 2.5v v out_ = 1.2v v out_ = 1.8v efficiency vs. load current with 2.5v input max8855/max8855a toc02 load current (ma) efficiency (%) 1000 10 20 30 40 50 60 70 80 90 100 0 100 10,000 v out_ = 1.2v v out_ = 1.8v switching frequency vs. r fsync max8855/max8855a toc03 r fsync (k ? ) switching frequency (khz) 12 600 800 1000 1200 1400 1600 1800 2000 2200 2400 400 369 151821 typical operating characteristics (v in1 = v in2 = 3.3v, max8855/max8855a, circuit of figure 6, t a = +25c, unless otherwise noted.)
max8855/max8855a dual, 5a, 2mhz step-down regulators _______________________________________________________________________________________ 5 switching frequency vs. temperature max8855/max8855a toc04 ambient temperature ( c) switching frequency (khz) 35 920 940 960 980 1000 1020 1040 1060 1080 1100 900 -40 -15 10 60 85 feedback voltage vs. temperature max8855/max8855a toc05 ambient temperature ( c) feedback voltage (mv) 35 592 594 596 598 600 602 604 606 608 610 590 -40 -15 10 60 85 shutdown supply current vs. supply voltage max8855/max8855a toc06 supply voltage (v) shutdown supply current (na) 3.10 1 2 3 4 5 6 7 8 9 10 0 2.35 2.60 2.85 3.35 3.60 i in1 + i in2 + i vdl + i vdd load transient max8855/max8855a toc07 20 s/div i out_ v out_ 1a/div 100mv/div 1.8v output 3.0a 1.5a 1.5a switching waveforms max8855/max8855a toc08 400ns/div i l2 i l1 v lx2 v lx1 2v/div 2v/div 2a/div 2a/div soft-start and shutdown max8855/max8855a toc09 400 s/div 3a load i in2 v out2 v pwrgd2 v en2 5v/div 2v/div 1v/div 1a/div typical operating characteristics (continued) (v in1 = v in2 = 3.3v, max8855/max8855a, circuit of figure 6, t a = +25c, unless otherwise noted.)
max8855/max8855a dual, 5a, 2mhz step-down regulators 6 _______________________________________________________________________________________ typical operating characteristics (continued) (v in1 = v in2 = 3.3v, max8855/max8855a, circuit of figure 6, t a = +25c, unless otherwise noted.) output tracking (en1 = en2) max8855/max8855a toc13 1ms/div ddr tracking 1.8v, 0.9v v out1 v out2 v pwrgd1 v pwrgd2 1v/div 1v/div 2v/div 2v/div external synchronization max8855/max8855a toc14 400ns/div v lx1 v lx2 2v/div 2v/div 2v/div pulse generator signal. a 10k ? resistor is connected between the pulse generator and fsync starting into prebiased output max8855/max8855a toc15 40 output peak current limit vs. output voltage max8855/max8855a toc10 output voltage (v) output peak current limit (a) 1.7 2.0 1 2 3 4 5 6 7 8 0 0.8 1.1 1.4 2.3 2.6 short circuit and recovery max8855/max8855a toc11 1ms/div i l1 v out1 500mv/div 2a/div 0a output sequencing (en2 = pwrgd1) max8855/max8855a toc12 1ms/div v out1 v out2 v pwrgd1 v pwrgd2 1v/div 1v/div 2v/div 2v/div
max8855/max8855a dual, 5a, 2mhz step-down regulators _______________________________________________________________________________________ 7 pin description pin name function 1 pwrgd1 power-good open-drain output for regulator 1. pwrgd1 is high impedance when v refin 0.54v and v fb1 0.9 x v refin . pwrgd1 is low when v refin < 0.54v, en1 is low, v dd or in1 is below uvlo, the thermal shutdown is activated, or when v fb1 < 0.9 x v refin . 2 refin external reference input for regulator 1. connect an external reference to refin, or connect refin to ss1 to use the internal reference. refin is discharged to gnd through 335 ? when en1 is low or regulator 1 is shut down due to a fault condition. 3v dd supply voltage. connect a 10 ? resistor from v dd to vdl and connect a 0.1f capacitor from v dd to gnd. 4 gnd analog ground. connect gnd to the analog ground plane. connect the analog and power ground planes together at a single point near the ic. 5 n.c. no connection 6 vdl supply voltage input for low-side gate drive. connect vdl to in_ or the highest available supply voltage less than 3.6v. connect a 1f capacitor from vdl to the power ground plane. 7 fsync frequency set and synchronization. connect a 4.75k ? to 20.5k ? resistor from fsync to gnd to set the switching frequency or drive with a 250khz to 2.5mhz clock signal to synchronize switching. r fsync = (t - 0.05s) x (10k ? /0.95s), where t is the oscillator period. 8 pwrgd2 power-good open-drain output for regulator 2. pwrgd2 is high impedance when v ss2 0.54v and v fb2 0.9 x v ss2 . pwrgd2 is low when v ss2 < 0.54v, en2 is low, v dd or in2 is below uvlo, the thermal shutdown is activated, or when v fb2 < 0.9 x v ss2 . 9 ss2 s oft- s tar t for reg ul ator 2. c onnect a cap aci tor fr om s s 2 to gn d to set the soft- star t ti m e. s ee the s etti ng the s oft- s tar t ti m e secti on. s s 2 i s i nter nal l y p ul l ed l ow w i th 335 ? w hen e n 2 i s l ow or r eg ul ator 2 i s i n a faul t cond i ti on. 10 fb2 feedback input for regulator 2. connect fb2 to the center of an external resistor-divider from the output to gnd to set the output voltage from 0.6v to 90% of v in2 . fb2 is high impedance when the ic is shut down. 11 comp2 compensation for regulator 2. comp2 is the output of the internal voltage-error amplifier. connect external compensation network from comp2 to fb2. see the compensation design section. comp2 is internally pulled to gnd when the output is shut down. 12 en2 enable input for regulator 2. drive en2 high to enable regulator 2, or drive low for shutdown. for always-on operation, connect en2 to v dd . 13, 14 in2 power-supply input for regulator 2. the voltage range is 2.35v to 3.6v. connect two 10f and one 0.1f ceramic capacitors from in2 to pgnd2. 15, 16, 17 pgnd2 power ground for regulator 2. connect all pgnd_ pins to the power ground plane. connect the power ground and analog ground planes together at a single point near the ic. 18, 19 lx2 inductor connection for regulator 2. connect an inductor between lx2 and the regulator output. lx2 is high impedance when the ic is shut down. 20 bst2 bootstrap connection for regulator 2. connect a 0.1f capacitor from bst2 to lx2. bst2 is the supply for the high-side gate drive. bst2 is charged from vdl with an internal pmos switch. in shutdown, there is an internal diode junction from lx2 to bst2 and from vdl to bst2. 21 bst1 bootstrap connection for regulator 1. connect a 0.1f capacitor from bst1 to lx1. bst1 is the supply for the high-side gate drive. bst1 is charged from vdl with an internal pmos switch. in shutdown, there is an internal diode junction from lx1 to bst1 and from vdl to bst1. 22, 23 lx1 inductor connection for regulator 1. connect an inductor between lx1 and the regulator output. lx1 is high impedance when the ic is shut down. 24, 25, 26 pgnd1 power ground for regulator 1. connect all pgnd_ pins to the power ground plane. connect the power ground and analog ground planes together at a single point near the ic.
max8855/max8855a dual, 5a, 2mhz step-down regulators 8 _______________________________________________________________________________________ 8 _______________________________________________________________________________________ pin description (continued) pin name function 27, 28 in1 p ow er - s up p l y inp ut for reg ul ator 1. the vol tag e r ang e i s 2.35v to 3.6v for the m ax 8855. the vol tag e r ang e i s 2.30v to 3.6v for the m ax 8855a. c onnect tw o 10f and one 0.1f cer am i c cap aci tor s fr om in 1 to p g n d 1. 29 en1 enable input for regulator 1. drive en1 high to enable regulator 1, or low for shutdown. for always-on operation, connect en1 to v dd . 30 comp1 compensation for regulator 1. comp1 is the output of the internal voltage-error amplifier. connect external compensation network from comp1 to fb1. see the compensation design section. comp1 is internally pulled to gnd when the output is shut down. 31 fb1 feedback input for regulator 1. connect fb1 to the center of an external resistor-divider from the output to gnd to set the output voltage from 0.6v to 90% of v in1 . fb1 is high impedance when the ic is shut down. 32 ss1 soft-start for regulator 1. connect a capacitor from ss1 to gnd to set the startup time. see the setting the soft-start time section. when e1 is disabled (pulled low), or regulator 1 is in shutdown mode due to a fault condition, ss1 is internally pulled low with 335 ? resistor. ep exposed pad. connect the exposed pad to the power ground plane. detailed description pwm controller the controller logic block is the central processor that determines the duty cycle of the high-side mosfet under different line, load, and temperature conditions. under normal operation, where the current-limit and temperature protection are not triggered, the control logic block takes the output from the pwm comparator and generates the driver signals for both high-side and low-side mosfets. it also contains the break-before- make logic and the timing for charging the bootstrap capacitors. the error signal from the voltage-error amplifier is compared with the ramp signal generated by the oscillator at the pwm comparator and, thus, the required pwm signal is produced. the high-side switch is turned on at the beginning of the oscillator cycle and turns off when the ramp voltage exceeds the v comp_ signal or the current-limit threshold is exceeded. the low-side switch is then turned on for the remainder of the oscillator cycle. the two switching regulators oper- ate at the same switching frequency with 180 phase shift to reduce the input-capacitor ripple current requirement. figure 1 shows the max8855/max8855a functional diagram. current limit the max8855/max8855a provide both peak and valley current limits to achieve robust short-circuit protection. during the high-side mosfets on-time, if the drain- source current reaches the peak current-limit threshold (specified in the electrical characteristics table), the high-side mosfet turns off and the low-side mosfet turns on, allowing the current to ramp down. at the next clock, the high-side mosfet is turned on only if the inductor current is below the valley current limit. otherwise, the pwm cycle is skipped to continue ramp- ing down the inductor current. when the inductor current stays above the valley current limit for 12s and the fb_ is below 0.7 x v refin , the regulator enters hiccup mode. during hiccup mode, the ss_ capacitor is discharged to zero and the soft-start sequence begins after a predeter- mined time period. undervoltage lockout (uvlo) when the v dd supply voltage drops below the falling undervoltage threshold (typically 1.9v), the max8855/ max8855a enter the undervoltage lockout mode (uvlo). uvlo forces the devices to a dormant state until the input voltage is high enough to allow the device to function reliably. in uvlo, lx_ nodes of both regulators are in the high-impedance state. pwrgd1 and pwrgd2 are forced low in uvlo. when v vdd rises above the rising undervoltage threshold (typically 2v), the ic powers up normally as described in the startup and sequencing section. the uvlo circuitry also monitors the in1 and in2 sup- plies. when the in_ voltage drops below the falling undervoltage threshold (typically 1.9v), the correspond- ing regulator shuts down, and corresponding pwrgd_ goes low. the regulator powers up when v in_ rises above the rising undervoltage threshold (typically 2v). power-good output (pwrgd_) pwrgd1 and pwrgd2 are open-drain outputs that indicate when the corresponding output is in regulation. pwrgd1 is high impedance when v refin 0.54v and v fb1 0.9 x v refin . pwrgd1 is low when v refin < 0.54v, en1 is low, v vdd or v in1 is below v uvlo , the thermal-overload protection is activated, or when v fb1 < 0.9 x v refin .
max8855/max8855a dual, 5a, 2mhz step-down regulators _______________________________________________________________________________________ 9 figure 1. functional diagram v dd pgnd1 lx1 in1 vdl bst1 en1 en2 ss2 refin fb1 comp1 ss1 shutdown control uvlo circuitry current-limit comparator dc dc ilim threshold ilim threshold bst cap charging switch v dd bias generator voltage reference ref from ss2 (0.6v) soft-start 1 error amplifier pwm comparator soft-start 2 vdl + - fb2 error amplifier + - - + +- - + pwm comparator shdn - + comp low detector comp2 comp low detector in1 in2 control logic clock thermal shutdown1 en1 lx1 in1 pgnd2 fsync lx2 in2 bst2 current-limit comparator bst cap charging switch +- - + + - control logic clock thermal shutdown2 en2 pwrgd1 lx2 in2 oscillator gnd clock + - fb1 0.9 x v refin refin ref 540mv shdn + - pwrgd2 + - fb2 0.9 x v ss2 ss2 540mv thermal shutdown thermal shutdown2 thermal shutdown1 max8855/max8855a
the power-good, open-drain output for regulator 2 (pwrgd2) is high impedance when v ss2 0.54v and v fb2 0.9 x v ss2 . pwrgd2 is low when v ss2 < 0.54v, en2 is low, v vdd or v in2 is below v uvlo , the thermal-over- load protection is activated, or when v fb2 < 0.9 x v ss2 . external reference input (refin) the max8855/max8855a have an external reference input. connect an external reference between 0 and v vdd - 1.6v to refin to set the fb1 regulation voltage. to use the internal 0.6v reference, connect refin to ss1. when the ic is shut down, refin is pulled to gnd through 335 ? . startup and sequencing the max8855/max8855a feature separate enable inputs (en1 and en2) for the two regulators. driving en_ high enables the corresponding regulator; driving en_ low turns the regulator off. driving both en1 and en2 low puts the ic in low-power shutdown mode, reducing the supply current typically to 30na. the max8855/max8855a regulators power up when the fol- lowing conditions are met (see figure 2): ? en_ is logic-high. ?v vdd is above the uvlo threshold. ?v in_ is above the uvlo threshold. ? the internal reference is powered. ? the ic is not in thermal overload (t j < +165c). once these conditions are met, the max8855/ max8855a begin soft-start. fb2 regulates to the volt- age at ss2. during soft-start, the ss2 capacitor is charged with a constant 8a current source so that its voltage ramps up for the soft-start time. see the setting the soft-start time section to select the ss2 capacitor for the desired soft-start time. fb1 regulates to the volt- age at refin. connect refin to ss1 to use the internal max8855/max8855a dual, 5a, 2mhz step-down regulators 10 ______________________________________________________________________________________ figure 2. startup control diagram uvlo uvlo therm shdn therm shdn ref bias gen ref rdy uvlo v dd rruvb rruvb rruvb en1 en2 reg1 on reg2 on uvlo uvlo tlim tlim in1 in2 figure 3a. startup and sequencing optionstwo independent output startup and shutdown waveforms en1 ss2 pwrgd1 en1 out1 out2 pwrgd2 en2 ss1 pwrgd2 v dd refin en2 en2 pwrgd1 10k ? 10k ? en1
max8855/max8855a dual, 5a, 2mhz step-down regulators ______________________________________________________________________________________ 11 figure 3b. startup and sequencing optionsratiometric tracking startup and shutdown waveforms v out1 track v out2 en out2 out1 pwrgd1 pwrgd2 out2 en1 ss2 pwrgd1 en2 ss1 pwrgd2 v dd refin 10k ? 10k ? 10k ? 10k ? en reference with soft-start time set independently by the ss1 capacitor (see figure 3a). for ratiometric tracking applications, connect refin to the center of a voltage-divider from the output of regula- tor 2 to gnd (see figure 3b). in this application, the en_ inputs are connected to each other and driven as a sin- gle enable input. regulator 2 starts up with a normal soft- start (c ss2 sets the time), and regulator 1 output ratiometrically tracks the regulator 2 output voltage. the voltage-divider resistors set the v out1 /v out2 ratio (see the setting the output voltage section). in figure 3b, v out1 regulates to half of v out2 . note that a capaci- tance of 1000pf should be connected to ss1 for stability. figure 3c shows the output sequencing application using an external reference. figure 3c. startup and sequencing optionssequencing startup and shutdown waveforms with external reference en1 out1 out2 pwrgd2 pwrgd1 en1 ss2 pwrgd1 en2 ss1 pwrgd2 v dd refin refin 10k ? 10k ? en1
sequencing is achieved by connecting en2 to pwrgd1. in this mode, regulator 2 starts once regulator 1 reaches regulation. in figure 3d, en1 and en2 are connected together and driven as a single input. although both outputs begin ramping up at the same time, slope matching is achieved by selecting the ss_ capacitors. see the setting the soft-start time section for information on selecting the ss_ capacitors. in figure 3d, the slope of the output voltages during soft-start is equal. this is achieved by setting the ratio of the soft-start capacitors equal to the ratio of the output voltages: synchronization (fsync) the max8855/max8855a operate from 500khz to 2mhz using either its internal oscillator, or an externally supplied clock. see the setting the switching frequency section. thermal-overload protection thermal-overload protection limits the total power dissi- pation of the max8855/max8855a. internal thermal sen- sors monitor the junction temperature at each of the regulators. when the junction temperature exceeds +165c, the corresponding regulator is shut down, allowing the ic to cool. the thermal sensor turns the reg- ulator on after the junction temperature cools by +20c. in a continuous thermal-overload condition, this results in a pulsed output. design procedure setting the output voltage the output voltages for regulator 1 (with refin con- nected to ss1) and regulator 2 are set with a resistor voltage-divider connected from the output to fb_ to gnd as shown in figure 4. select a value for the resis- tor connected from output to fb_ (r4 in figure 4) between 2k ? and 10k ? . use the following equations to find the value for the resistor connected from fb_ to gnd (r6 in figure 4): r v r out 6 06 06 4 = ? () . . _ c c v v ss ss out out 1 2 1 2 = max8855/max8855a dual, 5a, 2mhz step-down regulators 12 ______________________________________________________________________________________ figure 3d. startup and sequencing optionsmatching startup slopes of output voltages with internal reference en out1 out2 pwrgd2 pwrgd1 en en1 ss2 pwrgd1 en2 ss1 pwrgd2 v dd refin 10k ? 10k ? figure 4. type iii compensation network lx_ fb_ comp_ c o r4 r6 r7 c9 c11 l output r8 c10 max8855/ max8855a
max8855/max8855a dual, 5a, 2mhz step-down regulators ______________________________________________________________________________________ 13 in ddr tracking applications such as figure 7, the fb1 regulation voltage tracks the voltage at refin. in figure 7, the output of regulator 1 tracks v out2 , and the ratio of the output voltages is set as follows: setting the switching frequency the max8855/max8855a have an adjustable internal oscillator that can be set to any frequency from 500khz to 2mhz. to set the switching frequency, connect a resistor from fsync to gnd. calculate the resistor value from the following equation: the max8855/max8855a can also be synchronized to an external clock from 500khz to 2mhz by connecting the clock signal to fsync through a 10k ? isolation resistor. the external sync frequency must be higher than the frequency that would be produced by r fsync . the two regulators switch at the same frequency as the fsync clock, and are 180 out-of-phase with each other. the external clock duty cycle may range between 10% and 90% to ensure 180 out-of-phase operation. setting the soft-start time the two step-down regulators have independent adjustable soft-start. capacitors from ss_ to gnd are charged from a constant 8a (typ) current source to the feedback-regulation voltage. the value of the soft-start capacitors is calculated from the desired soft-start time as follows: inductor selection there are several parameters that must be examined when determining which inductor to use: maximum input voltage, output voltage, load current, switching frequency, and lir. lir is the ratio of inductor current ripple to dc load current. a higher lir value allows for a smaller inductor, but results in higher losses and higher output ripple. on the other hand, higher inductor values increase efficiency, but eventually resistive loss- es due to extra turns of wire exceed the benefit gained from lower ac current levels. a good compromise between size and efficiency is a 30% lir. for applica- tions in which size and transient response are impor- tant, an lir of around 40% to 50% is recommended. once all the parameters are chosen, the inductor value is determined as follows: where f s is the switching frequency. choose a standard value close to the calculated value. the exact inductor value is not critical and can be adjusted to make trade- offs among size, cost, and efficiency. find a low-loss inductor with the lowest possible dc resistance that fits the allotted dimensions. the peak inductor current is determined as: i peak must not exceed the chosen inductors saturation current rating or the minimum current-limit specification for the max8855/max8855a. input-capacitor selection the input capacitor for each regulator serves to reduce the current peaks drawn from the input power supply and reduces switching noise in the ic. the total input capacitance for each rail must be equal to or greater than the value given by the following equation to keep the input-voltage ripple within specifications and mini- mize the high-frequency ripple current being fed back to the input source: where d_ is the quiescent duty cycle (v out_ /v in_ ); f sw is the switching frequency; and v in_ripple_ is the peak-to-peak input-ripple voltage, which should be less than 2% of the minimum dc input voltage. the impedance of the input capacitor at the switching frequency should be less than that of the input source so high-frequency switching currents do not pass through the input source but are instead shunted through the input capacitor. high source impedance requires high-input capacitance. the input capacitor must meet the ripple current requirement imposed by the switching currents. the rms input ripple current, i ripple_ , is given by: iidd ripple out __ _( _) =? 1 c di fv in min out sw in ripple __ _ __ _ = i lir i peak out max =+ ? ? ? ? ? ? 1 2 () l vvv f v lir i out in out s in out max = ? () () ct a v ss ss _ . = ? ? ? ? ? ? 8 06 r f ns k ns fsync s =? ? ? ? ? ? ? ? ? ? ? ? ? 1 50 10 950 ? v v r rr out out 1 2 19 119 = +
output-capacitor selection the key selection parameters for the output capacitor are capacitance, esr, esl, and voltage-rating require- ments. these affect the overall stability, output ripple voltage, and transient response of the dc-dc convert- er. the output ripple occurs due to variations in the charge stored in the output capacitor, the voltage drop due to the capacitors esr, and the voltage drop due to the capacitors esl. calculate the output-voltage ripple due to the output capacitance, esr, and esl as: where the output ripple due to output capacitance, esr, and esl is: or: whichever is greater. it should be noted that the above ripple voltage compo- nents add vectrorially rather than algebraically, thus making v ripple a conservative estimate. the peak inductor current (i p-p ) is: use these equations for initial capacitor selection. determine final values by testing a prototype or an eval- uation circuit. a smaller ripple current results in less out- put-voltage ripple. since the inductor ripple current is a function of the inductor value, the output-voltage ripple decreases with larger inductance. use ceramic capaci- tors for low esr and low esl at the switching frequency of the converter. the low esl of ceramic capacitors makes ripple voltages due to esl negligible. load-transient response depends on the selected out- put capacitance. during a load transient, the output instantly changes by esr x ? i load . before the con- troller can respond, the output deviates further, depending on the inductor and output capacitor values. after a short time, the controller responds by regulating the output voltage back to its predetermined value. the controller response time depends on the closed-loop bandwidth. a higher bandwidth yields a faster response time, preventing the output from deviating fur- ther from its regulating value. see the compensation design and safe-starting into a prebiased output sec- tions for more details. compensation design the power-stage transfer function consists of one dou- ble pole and one zero. the double pole is introduced by the output filtering inductor, l, and the output filter- ing capacitor, c o . the esr of the output filtering capacitor determines the zero. the double pole and zero frequencies are given as follows: where r l is equal to the sum of the output inductors dc resistance and the internal switch resistance, r ds(on) . a typical value for r ds(on) is 35m ? . r o is the output load resistance, which is equal to the rated out- put voltage divided by the rated output current. esr is the total esr of the output-filtering capacitor. if there is more than one output capacitor of the same type in par- allel, the value of the esr in the above equation is equal to that of the esr of a single-output capacitor divided by the total number of output capacitors. the high-switching-frequency range of the max8855/ max8855a allows the use of ceramic output capacitors. since the esr of ceramic capacitors is typically very low, the frequency of the associated transfer-function zero is higher than the unity-gain crossover frequency, f c , and the zero cannot be used to compensate for the double pole created by the output filtering inductor and capacitor. the double pole produces a gain drop of 40db and a phase shift of 180 per decade. the error amplifier must compensate for this gain drop and phase shift to achieve a stable high-bandwidth closed-loop system. therefore, use type iii compensation as shown in figure 4. type iii compensation possesses three poles and two zeros with the first pole, f p1_ea , located at 0hz (dc). locations of other poles and zeros of type iii compensation are given by: f rc zea 1 1 279 _ = f esr c z esr o _ = 1 2 ff lc r esr rr plc p lc o o ol 12 1 2 __ == + + ? ? ? ? ? ? i vv fl v v pp in out s out in ? = ? v i t esl ripple esl pp off () = ? v i t esl ripple esl pp on () = ? v i esr ripple esr p p () = ? v i cf ripple c pp out s () = ? 8 vv v v ripple ripple c ripple esr ripple esl =+ + () ( ) ( ) max8855/max8855a dual, 5a, 2mhz step-down regulators 14 ______________________________________________________________________________________
max8855/max8855a dual, 5a, 2mhz step-down regulators ______________________________________________________________________________________ 15 these equations are based on the assumptions that c9 >> c10, and r4 >> r8, which are true in most applica- tions. placement of these poles and zeros is deter- mined by the frequencies of the double pole and esr zero of the power stage transfer function. it is also a function of the desired closed-loop bandwidth. figure 5 shows the pole zero cancellations in the type iii com- pensation design. the following section outlines the step-by-step design procedure to calculate the required compensation com- ponents. begin by setting the desired output voltage as described in the setting the output voltage section. the crossover frequency f c (or closed-loop, unity-gain bandwidth of the regulator) should be between 10% and 20% of the switching frequency, f s . a higher crossover frequency results in a faster transient response. too high of a crossover frequency can result in instability. once f c is chosen, calculate c9 (in farads) from the following equation: where v in is the input voltage in volts, f c is the crossover frequency in hertz, r4 is the upper feedback resistor (in ohms), r l is the sum of the inductor resis- tance and the internal switch on-resistance, and r o is the output load resistance (v out /i out ). due to the underdamped nature of the output lc double pole, set the two zero frequencies of the type iii com- pensation less than the lc double-pole frequency to provide adequate phase boost. set the two zero fre- quencies to 80% of the lc double-pole frequency. hence: set the third compensation pole, f p3_ea , at f z_esr , which yields: r c esr c o 8 11 = c r l c r esr rr oo lo 11 1 08 4 = + () + . r c l c r esr rr oo lo 7 1 08 9 = + () + . c v fr r r in c l o 9 25 241 = + ? ? ? ? ? ? . f rc pea 3 1 2811 _ = f rc pea 2 1 2710 _ = f rc zea 2 1 2411 _ = figure 5. pole zero cancellations in compensation design open-loop gain double poles third pole second pole first and second zeros power-stage transfer function compensation transfer function frequency gain
max8855/max8855a set the second compensation pole at 1/2 the switching frequency. calculate c10 as follows: the recommended range for r4 is 2k ? to 10k ? . note that the loop compensation remains unchanged if only r6s resistance is altered to set different outputs. safe-starting into a prebiased output the max8855/max8855a are capable of safe-starting up into a prebiased output without discharging the out- put capacitor. this type of operation is also termed monotonic startup. however, in order to avoid output voltage glitches during safe-start it should be ensured that the inductor current is in continuous conduction mode during the end of the soft-start period, this is done by satisfying the following equation: where c o is the output capacitor, v o is the output volt- age, t ss is the soft-start time set by the soft-start capac- itor c ss , and i p-p is the peak inductor ripple current (as defined in the output-capacitor selection section). depending on the application, one of these parameters may drive the selection of the others. see starting into prebiased output waveforms in the typical operating characteristics section for an example selection of the above parameters. applications information pcb layout guidelines careful pcb layout is critical to achieve low switching losses and clean, stable operation. the switching power stage requires particular attention. it is highly recommended to duplicate the max8855 ev kit layout for optimum performance. if deviation is necessary, fol- low these guidelines for a good pcb layout: ? a multilayer pcb is recommended. use inner-layer ground (and power) planes to minimize noise cou- pling. ? place the input ceramic decoupling capacitor directly across and as close as possible to in_ and pgnd_. this is to help contain the high switching currents within a small loop. ? connect in_ and pgnd_ separately to large copper areas to help cool the ic and further improve effi- ciency and long-term reliability. ? connect input, output, and vdl capacitors to the power ground plane (pgnd_). ? keep the path of switching currents short and mini- mize the loop area formed by lx_, the output capacitor(s), and the input capacitor(s). ? place the ic decoupling capacitors as close as possible to the ic pins, connecting all other ground- terminated capacitors, resistors, and passive com- ponents to the reference or analog ground plane (gnd). ? separate the power and analog ground planes, using a single-point common connection point (typi- cally, at the c in_ cathode. ? connect the exposed pad to the analog ground plane, allowing sufficient copper area to help cool the device. if the exposed pad is used as a com- mon pgnd_-to-gnd connection point, avoid run- ning high current through the exposed pad by using separate vias to connect the pgnd_ pins to the power ground plane rather than connecting them to the exposed pad on the top layer. ? use caution when routing feedback and compensa- tion node traces; avoid routing near high dv/dt nodes (lx_) and high-current paths. place the feed- back and compensation components as close as possible to the ic pins. ? reference the max8855/max8855a evaluation kit for an example layout. c v t i o o ss pp ? 2 c rf s 10 1 7 = dual, 5a, 2mhz step-down regulators 16 ______________________________________________________________________________________
max8855/max8855a dual, 5a, 2mhz step-down regulators ______________________________________________________________________________________ 17 figure 6. 1mhz typical application circuit max8855/ max8855a in2 pgnd2 c2 0.1 f bst2 lx2 c17 0.1 f c13 150pf r9 1k ? c23 10 f pwrgd2 fb2 gnd comp2 c19 22 f c20 0.1 f out2 1.8v/5a out1 1.2v/5a 2.30v to 3.6v (max8855a) pwrgd2 l2 0.56 h r10 27k ? c15 220pf ss2 c12 0.022 f c14 open v dd fsync refin ss1 r5 10k ? r13 40.2k ? r12 20k ? r10 20k ? in1 input 2.35v to 3.6v (max8855) pgnd1 c3 0.1 f bst1 lx1 c6 0.1 f c11 1000pf r8 200 ? c1 10 f fb1 comp1 c18 47 f c4 0.1 f l1 0.56 h c16 0.1 f r11 10 ? c8 0.22 f v dd r7 10k ? c9 330pf c10 open r4 10k ? r6 10k ? en2 en2 v dd pwrgd1 pwrgd1 v dd r15 20k ? c5 0.022 f en1 en1 exposed pad off on off on vdl
max8855/max8855a dual, 5a, 2mhz step-down regulators 18 ______________________________________________________________________________________ figure 7. tracking ddr application circuit max8855/ max8855a in2 pgnd2 pgnd2 c2 0.1 f bst2 lx2 c17 0.1 f c13 150pf r9 1k ? c23 10 f pwrgd2 fb2 gnd comp2 c19 22 f c20 0.1 f out2 1.8v/5a out1 0.9v/5a pwrgd2 l2 1 h r10 27k ? c15 220pf ss2 c12 0.022 f c14 open v dd fsync refin ss1 r5 5k ? r13 40.2k ? r12 20k ? r10 20k ? in1 input 2.35v to 3.6v for max8855 2.30v to 3.6v for max8855a pgnd1 c3 0.1 f bst1 lx1 c6 0.1 f c11 1000pf r8 200 ? c1 10 f fb1 comp1 c18 47 f c4 0.1 f l1 1 h c16 0.1 f r11 10 ? c8 0.22 f v dd r7 10k ? c9 330pf c10 open r4 10k ? r19 1k ? r1 1k ? en2 en2 v dd pwrgd1 pwrgd1 v dd r15 20k ? c7 1000pf en1 en1 exposed pad off on off on vdl out2
max8855/max8855a dual, 5a, 2mhz step-down regulators ______________________________________________________________________________________ 19 chip information process: bicmos max8855/ max8855a tqfn (5mm x 5mm) + top view 29 30 28 27 12 11 13 refin gnd n.c. vdl fsync 14 pwrgd1 lx1 bst1 bst2 pgnd1 lx2 lx2 12 in1 4567 23 24 22 20 19 18 en1 comp1 in2 in2 en2 comp2 v dd lx1 3 21 31 10 fb1 fb2 32 9 ss1 ss2 in1 26 15 pgnd2 pgnd1 25 16 pgnd2 pwrgd2 pgnd2 8 17 pgnd1 pin configuration package type package code outline no. land pattern no. 32 tqfn-ep t3255-4 21-0140 90-0012 package information for the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status.
max8855/max8855a dual, 5a, 2mhz step-down regulators maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 20 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2011 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 8/07 initial release 1 6/08 revised features section and corrected figure 6. 1, 17 2 4/09 revised features , typical operating characteristics , and output-capacitor selection sections. added the safe-starting into a prebiased output section. 1, 6, 14, 16 3 7/11 added the max8855a to the data sheet. added soldering temperature and package thermal characteristics to absolute maximum ratings . changed typical operating circuit . added new electrical characteristics table. changed input voltages in figures 6 and 7. 1, 2, 3, 16

▲Up To Search▲

Price & Availability of MAX8855AETJ

	To Download MAX8855AETJ Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .